Aedvices

Experimented SoC Design Engineer (M/F)

The position

As a key member of the design team (6 engineers), you will define the SoC architectures and specify the blocks to be developed. You are involved in ASIC development at the front end (Verilog and VHDL).

You collaborate with the verification team as well as with the backend teams of our partners and customers.

This position could be right for you if

You have an engineering or equivalent background and at least five years of experience with ASIC hardware conception.

Technical know-how

  • Multi-core System-On-Chip architecture
  • AMBA (AXI, APB, AHB, …) and On-Chip-Interconnect bus expertise
  • Network-on-Chip, performance analysis
  • Hardware/Software partionning
  • Complex block designs ( DMA, Interrupt Controllers, CPU, signal processing, … )
  • RTL design (Verilog or VHDL , SystemVerilog design)
  • Multiple Clock Domain design, CDC
  • STA / Timing Closure
  • Power aware design ( UPF / CPF )
  • Interaction with verification teams
  • Design Project Lead
  • Back end
  • DFT
  • P&R

Additional technical knowledge

  • English
  • V model
  • Quality standard (DO254, ISO 26262, …)

Soft skills

The ideal candidate should be curious and pro-active, have an appetite for technical challenges, enjoy learning for their own development and that of others.

You should also enjoy working as part of a team on a variety of projects and not shy away from technical challenges.

You should be open-minded, have good communication capacities and be creative.

Type of contract

Permanent full-time (39 hours per week with ten floating days off per year in addition to paid vacation time), profit-sharing (up to 10% of your base salary), position based at our head office in Moirans near Grenoble.

You can work out of the Grenoble or Paris areas or in the south of France (Provence Alpes Côte d’Azur region). Short trips to our customers’ premises in France and Europe may be required.

Compensation

According to profile

Start date

May-June 2022

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