As a key player and expert in the verification team (~10 engineers), you will define the verification methodologies adapted to the projects. You will be responsible for the verification of IPs and System-On-Chips, the development of verification environments (SystemVerilog/UVM/other), UVM verification IPs (VIPs) and the writing of verification plans.
You are required to supervise the juniors and make them increase their skills. Also, you propose improvements on existing flows and are an actor in the creation of training content. Depending on your profile, you may be required to provide training yourself. You will also have the opportunity to work with our partners on innovative approaches and methodologies (formal methods, PSS) and to intervene as a reference for the company in Accellera work groups.
This position could be right for you if
With an engineering background or equivalent, you have at least 5 years of significant experience in hardware verification and you are familiar with SystemVerilog and UVM. You have a technical sensitivity to both hardware and software.
- Expertise in SystemVerilog and UVM testbench development
- Experience in functional verification of complex IP and SoC
- Development of verification plans
- Knowledge of RTL design languages: VHDL, Verilog
- System-On-Chip architectures (AMBA bus, RiscV and/or ARM architecture)
- Object programming
- Knowledge of embedded software development (C, C++)
- Formal Verification / VAS
- ASIC and FPGA design
- Scripting (Python)
The ideal candidate should be curious and pro-active, have an appetite for technical challenges, enjoy learning for their own development and that of others.
Type of contract
Permanent full-time (39 hours per week with ten floating days off per year in addition to paid vacation time), profit-sharing (up to 10% of your base salary), position based at our head office in Moirans near Grenoble.
Short trips to our customers’ premises in France and Europe may be required.
According to profile