As a key member of the verification team (around 10 engineers), you will implement advanced verification solutions in conjunction with our EDA partners and our customers. You will develop complex multi-core test scenarios at SoC level in a SystemVerilog and UVM environment. You will contribute to the quality assurance of ASIC and FPGA developments for the energy, space, and IoT industries.
You will be the first user of the integrated circuits designed. Therefore, strong analytical skills and attention to detail are essential.
In your new position, you will receive support and training to skill up in SystemVerilog, UVM, verification methodologies, formal methods, and more.
This position could be right for you if
You have an engineering or equivalent background and at least two years of experience with SystemVerilog and UVM verification. The ideal candidate will also possess good technical knowledge of both hardware and software.
- SystemVerilog testbench and UVM development
- Simulation and debug with Modelsim, Questa, Xcelium, VCS
- Knowledge of RTL design languages: VHDL, Verilog
- System-on-chip architectures (AMBA bus, RiscV and/or ARM architectures)
- Object programming
- Knowledge of embedded software development (C, C++)
- ASIC, FPGA design
- Scripting (Python)
The ideal candidate should be curious and pro-active, have an appetite for technical challenges, enjoy learning for their own development and that of others.
You should also enjoy working as part of a team on a variety of projects and not shy away from technical challenges.
Type of contract
Permanent full-time (39 hours per week with ten floating days off per year in addition to paid vacation time), profit-sharing (up to 10% of your base salary), position based at our head office in Moirans near Grenoble.
You can work out of the Grenoble or Paris areas or in the south of France (Provence Alpes Côte d’Azur region). Short trips to our customers’ premises in France and Europe may be required.
You must have professional-level proficiency in English.
According to profile