You’re passionate about verification? So are we!
Aedvices is a company on a human scale with big ambitions, specialising in the design, development and verification of ASICs and SoCs.
A friendly atmosphere and technical expertise drive us in our outsourced projects, consultancy assignments, VIP developments and training courses (UVM, Formal, VPlan, AI, etc.).
We work in partnership with our clients in the automotive, big data, AI, space and energy sectors on projects such as:
- The verification of a programmable System-on-Chip dedicated to space applications,
- The verification of a Bluetooth Low Energy System-on-Chip.
As part of our growth, we are seeking five verification engineers with proven experience to strengthen our team of experts.
Your main responsibilities
As a key member of the verification team, you will be responsible for the quality of the verification delivered. You will define the verification methodologies and adapt them to the project requirements. You will be responsible for the verification of complex IPs and System-On-Chips, the development of verification environments (SystemVerilog/UVM/other), UVM verification IPs (VIPs), and the writing of verification plans.
Thanks to your deep knowledge of complex protocols (PCIe-CXL, AXI, Ethernet, …), you can be involved in the verification of advanced systems. You propose improvements to existing flows.
You will have the opportunity to collaborate with our partners on innovative approaches and methodologies (formal methods, PSS).
You will also manage junior engineers and make them acquire new skills.
Is the job right for you?
To carry out your missions, you need to master several essential technical topics:
- Functional verification at IP level and of complex SoC
- SystemVerilog testbench and UVM core development
- Development of verification plans
- Embedded software development (C, C++)
- System-on-chip architectures (ARM, RiscV)
- Interconnects et Network-On-Chip, AMBA protocols (AXI, AHB, APB, CHI, …)
- PCIe-CXL, Ethernet and Bluetooth advanced communication protocols
- Knowledge of RTL design languages: VHDL, Verilog
- Formal Verification / SVA
- Written and spoken English
Other skills welcome:
- Object Oriented Programming,
- ASIC and FPGA design,
- Scripting (Python).
For an efficient and fruitful collaboration, we expect you to:
- Have an engineering background or equivalent, and at least 5 years’ experience in verification,
- Be able to balance perfectionism and pragmatism!
- Be eager to learn new things, grow your skills and elaborate creative technical solutions,
- Be able to work in a team,
- Think “problem solving” and think “out of the box”,
- And last but not least: be committed to customers’ satisfaction.
What we offer you
- Continue to develop your expertise with the access of all our training materials
- Benefit from a flexible organization with the possibility of remote work
- Additional benefits such as meal voucher and dental health
- Full time contract located in France or Sweden
Want to join us?
Our recruitment process is simple:
After an initial call, you’ll meet with Agnès, our HR Manager, and Eric, our Verification Technical Director.
If your expectations match ours, the recruitment process concludes with a meeting with François or Sylvian, our CEOs.
