Wherever your integrated circuit project is within the development flow, we can provide you with a dedicated solution built to save you time and help control costs:

  • IP, subsystem, processor (RiscV), and DSP design
  • System/SoC development
  • Hardware/software co-verification
  • Firmware verification
  • Application development
  • Evaluation and qualification of your tools and methodology

Turnkey IC design and design verification

Our project managers and project team can take on a complete system, specific IP blocks or custom UVM verification IP development, whatever the most appropriate technical solution is, supporting you through design and execution.

Turnkey IC design and verification projects are managed using agile methods, with scheduled intermediary releases up to the final release.

We free you up from day-to-day project management issues, allowing you to focus on your core business. Aedvices’ fixed-price turnkey services help keep your project on budget.

IC design and verification consulting

Whether you are seeking added flexibility, temporary additional resources to respond to an increase in demand, or expert insights on a specific issue, Aedvices consulting services are your ideal option. Our consultants can work from our offices or with your team at your premises for the duration of your project.

The steps in the IC development process


Needs analysis


System specifications


System architecture


Module specifications




Verification and validation





A closer look at each step in the IC development process

Step 01
Needs analysis (feasibility study)

Your IC design and verification needs will depend to some degree on your target market. To ensure that your development project produces the expected results, we spend time with your people to understand the technical aspects of your product and draw up specifications.

Do you need to purchase equipment or licenses? What are your engineering and other staffing requirements for the project? We know the right questions to ask to cost out your project. For you, this means no surprise or added costs. Every detail is planned and budgeted for in advance.

Once the specifications and budget are complete, our people will provide detailed project schedule. You will receive a GANTT chart (a visual schedule) showing each milestone in the project schedule all the way through to your finished product design.

Step 02
System specification

Whatever market you are addressing, it is highly likely that you will have to comply with regulations of some kind. We factor in regulatory issues early on to ensure that your product is compliant.

We bring our experience with critical systems to your project, to assess the level of criticality and adjust the IC design flow accordingly.

Any chip or software whose failure can result in serious consequences is considered a critical system. We make sure that the design flow and methods used respond to the reliability and other requirements of your critical systems.

Step 03
System architecture

Our consultants translate your high-level specifications into a system architecture and the associated design specifications.

Step 04
IP block specifications

You may need an IP that is not commercially available to address a specific issue.

We can develop custom IPs and IP blocks for your integrated circuit development projects. Our engineers are fluent in Intel, ARM, and Xilinx architectures and will select the most appropriate solution for your product.

Aedvices IP blocks are fully customizable and reusable. A custom IP also allows you to focus on the proprietary value of your design, ensure maximum re-usability, and increase the profitability of your design flow.

We use hardware description languages like Verilog and VHDL to design synthesizable RTL.

We develop a specific architecture for your project based on a feasibility study. Then we code, complete the RTL simulation, synthesis, and place & route. While these steps are being done, our consultants also simulate the IP and complete system verification.

Step 05

The design is developed in RTL (VHDL, Verilog, or SystemVerilog).

Critical systems

Our design team is well-versed in the specific and particularly demanding requirements of the space, aeronautics, and automotive industries.

Modules and IP

If your project involves complete modules, we draw up the module specifications and do the RTL development in VHDL or Verilog.

SoCs and subsystems

We develop the system architecture and draw up the specifications. We can model the system in SystemC/TLM. Depending on the system specifications, we complete the top level of the design, the interconnect, and the power management integrations.


We handle the hardware/software partitioning of your system, the bitstream, and the prototyping board. Our engineers are fluent in Xilinx, Microsemi, and Intel programmable logic architectures.

ASICs (Application-Specific Integrated Circuits)

We develop the RTL for your design and complete simulation, synthesis, and place & route.

Do you have questions about IC design and verification?

Step 05
Verification & Validation (V&V)

The system design flow includes steps to ensure that specifications and design are aligned using design verification and validation tools.

Our engineers use the following verification processes:

  • Assertion based verification, formal verification
  • Coverage, metrics driven, UVM
  • Graph based verification, portable stimulus, system verification
  • Continuous integration
  • Requirements-based test plans

We follow the V Model, which includes a testing phase for each development stage, to deliver efficient, well-organized service.

SoC, FPGA, and other design verification requires analyzing your specifications. We thoroughly review the design specifications, the design objective specifications (DOS), and the architecture as written in your specifications. Change requests are processed as they come in. We use version control software to manage the project.

Next, we complete full verification of the system.

Our engineers verify the implementation of your system to ensure it aligns with your specifications. This process is repeated each time the specifications are updated. We master a wide range of programming languages and tools, and use the ones most appropriate for your project. Our toolbox includes: SystemVerilog/UVM, Specman, VHDL/Verilog/SystemC, and Python/Perl (cocotb/Python-UVM) for unit and integration testing.

Aedvices develops quality verification IPs (VIPs) to meet your needs. Our VIPs are designed with full debug, functional coverage, and protocol checkers, to help you optimize your verification tasks and speed up your verification process.

Our verification IPs are based on SystemVerilog and UVM. A straightforward native integration and compilation flow ensures seamless integration into your SystemVerilog/UVM flow. Our Verilog procedures are easy to use, so that even designers can use our VIPs for directed testing.

If you are looking for solutions to speed up your network-on-chip, cache coherence, SoC embedded bus protocol, or SoC I/O protocol verification tasks, our VIPs can help.

  • Our VIPs are provided with their source code. They remain available to you for modification and reuse during future development projects.
  • They are compatible with SystemVerilog and UVM.
  • Aedvices VIPs can be customized to meet your needs.
  • On-Chip-Bus
    • AXI 3 & 4, AXI-ACE, CHI, ATB
    • APB, AHB
  • Generic SPI, Quad-SPI, UART
  • Generic NoC Verification IP

Our verification framework manages regressions of each sub-block and of the complete system. And, to improve project development quality and reduce risk, our framework is based on the Continuous Integration (CI) workflow and methodology.

Step 06

Aedvices uses agile project management methods. For critical systems, we document and ensure full traceability of all tests to meet the particular reliability and other requirements of these systems. We provide you with test reports so that you can ensure alignment with your KPIs.

Step 07

We provide additional documentation upon completion of your project.

For agile projects, intermediate deliverables will also be provided depending on sprints and any other needs you have expressed.

These documents are essential to the effective management of your project and include:


The project archive for handoff to your people for the next steps in your project and integration into your products.


Test reports documenting that the tests were completed, with a list of bugs and fixes.


Coverage reports indicating the test coverage rates.

These deliverables will ensure that you can test any subsequent changes to the project thoroughly.

In short, all verification documentation (verification plan, status report, final report) will be submitted to you. We also provide a bug report and recommendations for improving your architecture.

KVCA: Key Verification Capability Assessment

Aedvices offers KVCA services.

If your team includes verification engineers, you most likely already have a verification process in place. We can assess your process and help you improve it.

Our KVCA services include:

  • Process analysis: We appraise each step in your project management process, from the verification plan to the final report. We also examine how each of these steps fits into the project as a whole.
  • Analysis of interactions between development and business experts: From project managers to design and verification engineers, we look at who your project stakeholders are, how they interact, and any biases you need to be aware of. We assess whether their knowledge is sufficient for an optimized verification process.
  • Market/industry analysis: We look at your verification plan in light of any standards, regulations, or other requirements specific to your market or industry. Is your process based on functional aspects? Does it ensure traceability? Are metrics built into the process?
  • Review of current verification environments: We assess your current verification environments for accessibility, factorization, and reuse, and evaluate your implementation of test validation criteria.

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