IC design and IC design verification training
Aedvices UVM and SystemVerilog training courses can be tailored to your needs. Skill up your IC design engineers with Aedvices!
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Next sessions
SystemVerilog for Verification (SV4DVE)
From 27 May to 4 July 2025
- Kick-off : 27 May 2025
- Lives Integration : 10 and 24 June
- Workshops : 3 and 4 July
Access to online content at any time
UVM fundamentals for Verification (UVM-starter)
From 13 May to 27 June 2025
- Kick-off : 13 May
- Lives Integration : 27 May, 10 June and 24 June
- Workshops : 26 and 27 June
From 8 July to 19 September 2025
- Kick-off : 8 July
- Lives Integration : 29 July, 26 August and 16 September
- Workshops : 18 and 19 September
Access to online content at any time
High demand for IC design and verification skills
Verification engineers were few and far between just a decade ago. Now, on most integrated circuit design projects, verification engineers outnumber design engineers. According to the 2020 Wilson Research Group Functional Verification Study, more than half the time spent on IC design projects is spent on verification.
And yet only a small number of engineering schools offer courses in verification. There is a shortage of verification engineers on the job market, and companies are looking for ways to train their current engineers.
Aedvices IC design and verification training courses are modular and customizable to meet your engineers’ skills development needs.
UVM, a major IC design verification tool
Supported by the main EDA suppliers, UVM (Universal Verification Methodology) is a standardized verification methodology developed in SystemVerilog that allows you to develop test sequences and automate tests.
UVM is also used for the verification of circuit behavior, comparing output with specifications.
UVM and SystemVerilog training targeted audience
Microelectronics and FPGA design engineers whose job tasks include verification.
Verification engineers who want to improve their knowledge of verification methodology.
Managers who want to gain a better understanding of verification.
Our UVM and SystemVerilog courses are developed and delivered according to a formal quality management policy. For organizations in France, Aedvices has obtained Qualiopi quality certification for its training development and delivery processes.
Each training module addresses a specific IC design or verification skillset
We have developed a comprehensive set of IC design and verification training modules with specific learning outcomes. After each module, learners will know how to:
- Determine the best verification strategy for each project.
- Complete verification of IPs and SoCs.
- Develop verification environments (SystemVerilog/UVM) and UVM verification IPs (VIPs).
- Use formal verification to ensure whether the design satisfies requirements.
- Produce written verification plans.
- Develop complex multi-core test scenarios at SoC level in a SystemVerilog and UVM environment.
- Work on front-end ASIC development in SystemVerilog.
Here is a selection of our UVM and SystemVerilog training modules:
Training for verification engineers
- SystemVerilog basics
- Introduction to UVM
- SystemVerilog and UVM (advanced)
- UVM toolbox
- IP and SoC verification methodology
- Verification project planning and management
For design engineers
- Fundamentals of UVM in practice
- RTL design in SystemVerilog
Ask about our UVM training and SystemVerilog training today!
A unique teaching method: the MILLI-group structure
Aedvices, in collaboration with Iconda, has implemented a new teaching method, based on a unique format : the MILLI structure (Modular Independent Learning with Live Integration). With new expectations from trainees, we took the best of both eLearnings and live sessions.
Each participant will benefit from the best of breadth of:
A personal expert trainer available during the whole training to share expertise, to help in consolidation of independent work and to keep the student motivate.
Independent Learning (IL) (Asynchronous learning):
At each student pace, he/she will get access to :
– interactive online content with integrated video and quizzes, available at any time thanks to the Learning Management System (LMS)
– individual exercises and labs, with answers automatically sent to trainers for personalized follow-up.
– real-time instant messaging to our trainers to answer a question.
Live Integration (LI) (Synchronous learning):
Live sessions animated by an Aedvices expert:
– in-depth Question & Answer sessions in groups of up to 5.
– team-based workshops.
What is the MILLI-group structure?
Participants register for a given Module (see list of available modules).
Each Module is a combination of one or more sections (Independent Learning + Live Integration) and workshops.
A MILLI-group is up to 5 students.
The MILLI-group structure, the best of breadth of both asynchronous and synchronous learning methods
– More flexible scheduling and individual work plan
– Contact and interaction time is concentrated on the valuable topics
– Better student/trainer ratio in live sessions to improve interactions
– A new Learning Management System with a dedicated trainer to follow students progression.
All Aedvices training modules will be transitionning into the MILLI-Group trainning organisation during first half of 2024. Please enquire with your Aedvices representative the exact availability date of your module of interest.
The MILLI trainings in 5 key points:
This custom program is designed to be agile, with classes on theory and practice, as well as individual mentoring and coaching. Our trainers use innovative, adaptive, project-based methods to ensure that learners acquire and can apply new knowledge:
05
Checkpoints as a final activity to demonstrate newly acquired expertise (oral presentation of written work and of a case study).
01
Courses in video format for theoretical content, continuously available through eLearning.
02
Quiz, exercices and labs to move from theory to practice.
03
An expert trainer for personnal follow-up during the whole training.
04
Live sessions in group of up to 5 to ensure maximum interaction and optimal quality of exchanges.
Typically, learners spend around 25% of their time on theory and practice (classes and workshops), 25% on mentoring from their assigned mentor and the verification community, and 50% applying their new knowledge to a project at work.
Spotlight on the STMicroelectronics Verification School
Semiconductor manufacturer STMicroelectronics ran its own Verification Schools with us since 2019.
We set up a team of verification managers, trainers, and human resources professionals to custom-build the program.
The STMicroelectronics Verification School included classes at the company premises and, in some cases, outside the company, depending on the expected learning outcomes. Learners were assessed continuously so that training content and follow-up could be realigned with objectives at all times.
Our custom IC design and verification training process
01.
Needs analysis
Our training consultant meets with you to discuss your company’s employee training needs and objectives.
02.
Learning objectives
The expected learning outcomes of your training program depend on your situation. Are you onboarding new hires? Upskilling your current engineering staff? We make sure we understand exactly what you need and that the proposed content for your course is appropriate for your learners.
03.
Prerequisites
Some course modules have prerequisites. We help you make sure that your employees have the required prior knowledge to get the most of their course.
04.
Course creation
We create a custom course designed to meet your needs and ensure that the expected learning outcomes are achieved.
Teaching methods and tools
Learners are able to understand and experiment using the concepts addressed during the course through a sequence of theoretical classes and practical workshops.
Printed course materials is available on the LMS so that learners can easily find the information they need.
Learners also have access to video content on our LMS (learning management system) for one year after completion of the training.
Our trainers are approachable and available to answer learners’ questions. They help trainees apply new concepts to their own projects.
All of our courses are designed to be delivered to groups, orally, and with visual materials. Contact us to discuss any disabilities or other special needs your learners have so that we can make any necessary adaptations. There may be an additional cost for some adaptations.
Courses usually start around a month after the initial request.
The Aedvices LMS for continued learning after your course ends
The Aedvices LMS (learning management system) is an online portal where learners can access their course content for one year after their course ends.
Learners can go back to all of the modules they have completed at any time during the year.
The participant has access access to videos of all the modules followed thanks to a personalized account.
The trainer answers participants' questions via instant messaging.
Learners can apply their new knowledge in our online Labs.
Last but not least, learners can take quizzes to check their knowledge.
The Aedvices LMS ID and password are strictly personal and may be used only by the learner to whom they are assigned. Learners can print or make copies of the materials for their personal use only. All other reproduction or use of the materials is strictly prohibited.
Our trainers
Our trainers are experts in IP & SoC verification and are capable of adapting to learners’ prior knowledge and specific needs.
Meet some of our trainers
François is a verification expert and member of the Accellera Systems Initiative, an EDA and IC design and manufacturing standards organization. He consults with, trains, and advises verification project teams at companies across Europe. He is also one of our training quality assurance coordinators.
Consultant and verification expert for Systemverilog/UVM, Eric is involved in the verification of complex systems. He is Verification Technical Director for Aedvices’ teams in France and Brazil. As a real globetrotter, he is highly adaptable, both in human and technical terms.
Aedvices training in a nutshell
(2019 to date)
23 courses delivered
+300 participants
50 modules developed
92% satisfaction rate*
100% of our courses can be delivered remotely
* (percentage of 125 participants that answered “yes” when asked “Did the program meet your expectations?”)
Our UVM and SystemVerilog training courses
The following information applies to all of our courses:
Languages
Courses can be taught in English or French; however, the materials are in English
Dates
Dates can be set to meet your needs
Trainer
Verification engineer
Teaching methods
- Classes on theory
- Case studies and practical application
- Personalized mentoring and coaching
Training management
- Attendance sheet
- Satisfaction survey
- Certificate of completion
Evaluation methods
Self-evaluation questionnaire available throughout the course and a final evaluation
To which training course apply?
Audience
Design Verification Engineers willing to learn SystemVerilog to develop testbenches or prior to join a UVM training
Objectives
Gain a basic working knowledge on SystemVerilog.
Know how to use the principal aspects of the SystemVerilog language used in verification.
Be able to build SystemVerilog testbenches using random generation and functional coverage
Prerequisites
Experience in using either Verilog or VHDL language for design or for building testbenches (ideally verilog)
* General programming knowledge: data types, loops, procedural programming such as C, Python, Perl, …
* Basic knowledge of object-oriented programming is a plus but is not strictly required
Next Sessions
- From 27 May to 4 July
Audience
Designers with Verilog or VHDL Background willing to use SystemVerilog to develop their designs
Objectives
Be able to use SystemVerilog design constructs
* to simplify my RTL designs
* to be more productive
* to understand what I’m doing
Know the principal SystemVerilog constructs used to build testbenches
Prerequisites
Have a VHDL design experience of over 1 year and have followed a training “Verilog for VHDL Designers” or equivalent
Have a Verilog design experience of over 1 year
Audience
Design Engineers willing to add assertions to improve their productivity.
Objectives
Be able to use SVA assertions as part of the RTL design process
Be able to check design intent using SVA
Know the different types of assertions
Be able to use immediate (boolean) assertions within the code
Be able to use concurrent assertions to check time consuming events
Prerequisites
Designers with RTL experience in Verilog
* Be able to write Verilog RTL designs
* Basic notions of C Programming
Audience
Verification Engineers starting with UVM
Objectives
Be able to work on UVM projects
Be able to instantiates and use a UVM Verification IP
Be able to write UVM sequences
Be able to implement a scoreboard
Be able to write simple UVM agent
Prerequisites
Having knowledge in SystemVerilog for verification (classes, interfaces, random generation, covergroups)
Next Sessions
- From 13 May to 27 June
- From 8 July to 19 September
Audience
Verification Engineers with a first experience in UVM willing to solve complex verification problem
Objectives
Be able to develop advanced sequences
* using the sequence arbitration scheme
* using random selections
* building sequence libraries
* building reactive sequences
Be able to develop a complete Verification IP from scratch
Be able to implement a Register Abstraction Layer prediction and connect it to a scoreboard
Be able to interface UVM with external C models
Prerequisites
Have a confirmed experience in using UVM
Audience
Students of the Verification School program
Objectives
Know what is verification
Have notions of verification planning and processes
Have basic TCL scripting compentences
Be able to work on projects using AMBA buses
Prerequisites
General hardware design and architecture knowledge
Some notions on test and verification
General project management know-how
Audience
This training is targeting verification engineers willing to acquire project management know-how and to be in a position to develop a verification plan.
An ideal training for Verification Engineers moving to responsibilities in verification projects and verification planning.
Objectives
Be able to define a verification strategy:
Know the main aspects of verification projects
Be able to define verification objectives, metrics and activities
Be able to develop a verification plan at IP and at SoC level
Be able to define KPIs and track a verification project progress
Prerequisites
General engineering background in hardware design and SoC architecture
Be involved in a hardware design and/or a verification project
Some notions of test and verification
General Project Management Know-How
Audience
Digital Microelectronics Engineers starting with SystemVerilog and UVM
Objectives
Be able to instantiate Verification IPs and create a UVM testbench.
Be able to implement coverage metrics in line with a verification plan to report verification progress
Be able to implement checkers using scoreboards and simple assertions
Prerequisites
General hardware design and architecture knowledge
Basic scripting know-how
Basic programming know-how (C, Python, …)
Knowledge of a Hardware Description Language such as VHDL or Verilog
Simulation know-how
Audience
Engineers with a first UVM experience willing to leverage their skills to resolve complex problems
Objectives
Be able to implement a Verification IP
Be able to implement a register abstraction layer and prediction
Be able to write complex random test sequences
Be able to use the DPI-C efficiently to connect to a reference model or to control a sequence
Prerequisites
Have experiences in writing test sequences
Be able to instantiate and use a Verification IP or a UVM agent
Be able to implement a scoreboard
Have notions of C programming
Audience
Verification Engineers moving to formal verification to verify critical functionalities
Objectives
Develop a formal verification approach and know-how to prove complex assertions using formal tools
Be able to develop complex assertions in SVA
Prerequisites
For verification engineers involved or planning to be involved in Formal Verification
Audience
For IP Verification Engineers willing to move to the SoC Level Verification level
For Verification Engineers starting a project at SoC Level
Objectives
Be able to develop SoC Level test following a verification plan
Be able to develop software driven tests at SoC Level
Be able to implement test automation at SoC Level
Understand how and why to use UVM at SoC Level
Be able to use coverage metrics and assertions at SoC Level
Prerequisites
For engineers involved in SoC Level Verification :
General hardware design and architecture knowledge
General knowledge on SoC architecture
Financing for your UVM training and SystemVerilog training
Qualiopi quality certification for training providers in France
Aedvices obtained Qualiopi quality certification to:
- Provide evidence of the quality of our training development and delivery processes
- Demonstrate our professionalism as a training provider
- Provide companies and training participants with clear information about our trainings
Because Aedvices is a Qualiopi-certified training provider, our trainings may be eligible for financing through the training fund you or your company are affiliated with. Contact your HR department to find out how to apply for financing.
Aedvices is Qualiopi-certified for its training activities.