IC design and IC design verification training
Aedvices UVM and SystemVerilog training courses can be tailored to your needs. Skill up your IC design engineers with Aedvices!
High demand for IC design and verification skills
Verification engineers were few and far between just a decade ago. Now, on most integrated circuit design projects, verification engineers outnumber design engineers. According to the 2020 Wilson Research Group Functional Verification Study, more than half the time spent on IC design projects is spent on verification.
And yet only a small number of engineering schools offer courses in verification. There is a shortage of verification engineers on the job market, and companies are looking for ways to train their current engineers.
Aedvices IC design and verification training courses are modular and customizable to meet your engineers’ skills development needs.
UVM, a major IC design verification tool
Supported by the main EDA suppliers, UVM (Universal Verification Methodology) is a standardized verification methodology developed in SystemVerilog that allows you to develop test sequences and automate tests.
UVM is also used for the verification of circuit behavior, comparing output with specifications.
Who is our UVM and SystemVerilog training for?
Microelectronics and FPGA design engineers whose job tasks include verification.
Verification engineers who want to improve their knowledge of verification methodology.
Managers who want to gain a better understanding of verification.
Our UVM and SystemVerilog courses are developed and delivered according to a formal quality management policy. For organizations in France, Aedvices has obtained Qualiopi quality certification for its training development and delivery processes.
Each training module addresses a specific IC design or verification skillset
We have developed a comprehensive set of IC design and verification training modules with specific learning outcomes. After each module, learners will know how to:
- Determine the best verification strategy for each project.
- Complete verification of IPs and SoCs.
- Develop verification environments (SystemVerilog/UVM) and UVM verification IPs (VIPs).
- Use formal verification to ensure whether the design satisfies requirements.
- Produce written verification plans.
- Develop complex multi-core test scenarios at SoC level in a SystemVerilog and UVM environment.
- Work on front-end ASIC development in SystemVerilog.
Here is a selection of our UVM and SystemVerilog training modules:
Training for verification engineers
- SystemVerilog basics
- Introduction to UVM
- SystemVerilog and UVM (advanced)
- UVM toolbox
- IP and SoC verification methodology
- Verification project planning and management
For design engineers
- Fundamentals of UVM in practice
- RTL design in SystemVerilog
Ask about our UVM training and SystemVerilog training today!
Our UVM and SystemVerilog courses are available in two formats:
In-company UVM training
Let us develop a custom UVM training course for your company.
We work together to set the most suitable course content and set a time and place that work for you. And, because our trainers come to your premises, you save on travel costs. Group sizes are kept small (under ten people) to ensure learners can actively engage and receive individualized attention.
Custom UVM training
Our custom, modular UVM training focuses on design verification, with modules addressing all aspects of the verification flow.
Our experts teach the latest methods and best practices. Custom training packages can also include a Key Verification Capabilities Assessment (KVCA) to assess your existing design verification infrastructure and make recommendations for improvement.
The Verification School Program
This custom program is designed to be agile, with classes on theory and practice, as well as individual mentoring and coaching. Our trainers use innovative, adaptive, project-based methods to ensure that learners acquire and can apply new knowledge:
01
Classroom sessions (in person or remote) to cover the main theoretical content.
02
Workshops to move from theory to practice.
03
Self-directed learning on real projects at work and through e-learning modules.
04
Mentoring with in-house senior verification engineers and outside experts.
05
A final written report and oral presentation (a case study) demonstrating mastery of the course content.
Typically, learners spend around 25% of their time on theory and practice (classes and workshops), 25% on mentoring from their assigned mentor and the verification community, and 50% applying their new knowledge to a project at work.
Spotlight on the STMicroelectronics Verification School
Semiconductor manufacturer STMicroelectronics ran its own Verification Schools with us since 2019.
We set up a team of verification managers, trainers, and human resources professionals to custom-build the program.
The STMicroelectronics Verification School included classes at the company premises and, in some cases, outside the company, depending on the expected learning outcomes. Learners were assessed continuously so that training content and follow-up could be realigned with objectives at all times.
Our custom IC design and verification training process
01.
Needs analysis
Our training consultant meets with you to discuss your company’s employee training needs and objectives.
02.
Learning objectives
The expected learning outcomes of your training program depend on your situation. Are you onboarding new hires? Upskilling your current engineering staff? We make sure we understand exactly what you need and that the proposed content for your course is appropriate for your learners.
03.
Prerequisites
Some course modules have prerequisites. We help you make sure that your employees have the required prior knowledge to get the most of their course.
04.
Course creation
We create a custom course designed to meet your needs and ensure that the expected learning outcomes are achieved.
Teaching methods and tools
Learners are able to understand and experiment using the concepts addressed during the course through a sequence of theoretical classes and practical workshops.
The trainer provides printed course materials at the beginning of face-to-face courses so that learners can easily find the information they need.
Learners also have access to video content on our LMS (learning management system) for one year after completion of the training.
Our trainers are approachable and available to answer learners’ questions. They help trainees apply new concepts to their own projects.
All of our courses are designed to be delivered to groups, orally, and with visual materials. Contact us to discuss any disabilities or other special needs your learners have so that we can make any necessary adaptations. There may be an additional cost for some adaptations.
Courses usually start around a month after the initial request.
The Aedvices LMS for continued learning after your course ends
The Aedvices LMS (learning management system) is an online portal where learners can access their course content for one year after their course ends.
Learners can go back to all of the modules they have completed at any time during the year.
Video recordings of live classes previously attended are also available.
An FAQ section offers easy access to answers to many questions learners ask.
Learners can apply their new knowledge in our online Labs.
Last but not least, learners can take quizzes to check their knowledge.
The Aedvices LMS ID and password are strictly personal and may be used only by the learner to whom they are assigned. Learners can print or make copies of the materials for their personal use only. All other reproduction or use of the materials is strictly prohibited.
Our trainers
Our trainers are experts in IP & SoC verification and are capable of adapting to learners’ prior knowledge and specific needs.
Meet some of our trainers
François Cerisier
François is a verification expert and member of the Accellera Systems Initiative, an EDA and IC design and manufacturing standards organization. He consults with, trains, and advises verification project teams at companies across Europe. He is also one of our training quality assurance coordinators.
Key strength:
attention to detail
Jordan Yon
Jordan is a SystemVerilog/UVM verification consultant and expert. His focus is complex systems verification for telecommunications and industrial projects. Most of his direct reports come from microelectronics or computer science. Keeping their skills up to date is part of his job. His trainees appreciate his ability to adapt to different levels and learning styles.
Key strength:
technical expertise
Ajeet Kumar
Ajeet is one of our senior consultants. He does IP verification for multimedia, telecommunications, and embedded software projects. He is an expert in SystemVerilog and UVM, part of his everyday toolbox. His experience and skills make him a valuable asset to any training course.
Key strength:
experience
Aedvices training in a nutshell
(2019 to date)
23 courses delivered
+200 participants
35 modules developed
92% satisfaction rate*
100% of our courses can be delivered remotely
* (percentage of 125 participants that answered “yes” when asked “Did the program meet your expectations?”)
Our UVM and SystemVerilog training courses
The following information applies to all of our courses:
Languages
Courses can be taught in English or French; however, the materials are in English
Dates
Dates can be set to meet your needs
Trainer
Verification engineer
Teaching methods
- Classes on theory
- Case studies and practical application
- Personalized mentoring and coaching
Training management
- Attendance sheet
- Satisfaction survey
- Certificate of completion
Evaluation methods
Self-evaluation questionnaire available throughout the course and a final evaluation
Verification fundamentals : SystemVerilog for verification
TM101
Verification fundamentals : Introduction to verification using UVM
TM102
UVM awareness for design engineers
TM201
UVM know-how for verification engineers
TM202
UVM toolbox for verification engineers
TM210
IP&SoC verification methodology with SystemVerilog and UVM
TM301
Advanced verification using SystemVerilog and UVM
TM250
Financing for your UVM training and SystemVerilog training
Qualiopi quality certification for training providers in France
Aedvices obtained Qualiopi quality certification to:
- Provide evidence of the quality of our training development and delivery processes
- Demonstrate our professionalism as a training provider
- Provide companies and training participants with clear information about our trainings
Because Aedvices is a Qualiopi-certified training provider, our trainings may be eligible for financing through the training fund you or your company are affiliated with. Contact your HR department to find out how to apply for financing.
Aedvices is Qualiopi-certified for its training activities.