Finite State Machine Verification Should Not Be Daunting: Govern It with an Explicit FSM
FSM verification feels daunting not because FSMs are inherently unmanageable, but because the verification method becomes opaque. What needs to become governable again is the verification work itself: what has been exercised, what remains outside that exercised behavior, and how changes affect the path to coverage. Making the FSM explicit as a graph restores the […]
Hardware–Software Co‑Verification: Why system‑level verification is no longer optional
In System‑on‑Chip development, most late‑stage issues are not caused by broken IPs or incorrect RTL logic. They are caused by integration assumptions that silently fail when software starts running on real hardware. This is not a marginal observation; it is a recurring reality across SoC projects. As designs grow in complexity, verifying hardware in isolation […]
From high-level specification to requirements: securing next-gen SoC success
Our client, a blue-chip company in smart energy systems was entering a critical phase: the development of a custom SoC to boost performance and differentiation in their next-generation product by integrating more digital processing into the architecture. To support this evolution, our client selected a major chip maker. Its role was to scale-up from a […]
From Proof-of-Concept to industrial embedded system: a full-cycle FPGA SoC project
How can an FPGA prototype based on an academic concept be developed into a complete industrial embedded solution? This case study presents a project carried out by our team. The objective of this mission was to transform an existing FPGA prototype into a robust, reliable digital platform. The next step was to make this platform […]
Aedvices Partners with Pyxalis to create a new CPU architecture
In spring 2023, Aedvices and Pyxalis brought together their technical skills and their application vision to demonstrate the relevance of an innovative architecture in image sensors. The goal of this collaboration was to validate the integration of this architecture into Pyxalis image sensors to improve performance. Specific attention has been paid to optimizing cache memory […]
Neurxcore leverages Aedvices VIPs for the verification of its neural processors
Neurxcore, a leading provider of optimized solutions for artificial intelligence (AI), has just announced the launch of a complete range of neural processors (NPUs) developed and verified using Aedvices’ VIPs. To ensure the quality of their IPs, Neurxcore has selected Aedvices for the use of its dedicated Verification IP (VIP). “Our SNVDLA neural processors are […]
The ST Verification School or how to solve the need for Verification engineers
When thinking of microelectronics engineering, you may think hardware, firmware and maybe software development activities. You may not think, however, of verification engineers even if they are key elements in a team. Verification engineers develop and implement testing procedures to determine if a product works as intended. As the verification of complex FPGAs and ASICs […]
The ST Verification School or how to solve the need for Verification engineers
When thinking of microelectronics engineering, you may think hardware, firmware and maybe software development activities. You may not think, however, of verification engineers even if they are key elements in a team. Verification engineers develop and implement testing procedures to determine if a product works as intended. As the verification of complex FPGAs and ASICs […]