Digital Design Engineer

Are you willing to join a fast-growing company, where your contribution to the team will be visible?

Do you share our values of Diversity, Conviviality, Technical Expertise and Passion?

Located in the Grenoble metropolitan area, the French capital of innovation, Aedvices specializes in ICs, FPGAs and embedded systems Front-End Digital Design and Design Verification. We provide flexible solutions to our customers, ranging from turnkey design and verification options to dedicated consulting in Design or verification.

Our customer base spans from large semiconductor groups to small tech startups

We support a wide range of projects in the automotive, big-data, artificial intelligence and energy sectors, such

  • The design of the control and acquisition systems of a weather satellite,
  • The design of IPs dedicated to datacenters performance,
  • The verification of the telemetry system of a Mars probe / Mars tremors,
  • The verification of a System-on-Chip for Bluetooth Low Energy.

To sustain our growth, we are looking for several digital design engineers to join the team.

Working environment

Reporting into the technical director, you will join our R&D team and work on our customers’ projects from our premises or remotely.

“I really enjoyed my first weeks with the company and the support I got during this period. I like working for a company that is expert in its field, where there’s a very good working atmosphere and a caring attitude. From the very first discussion, I felt at ease and already integrated into the team”, Christophe, Senior Design Engineer.

The key ingredients of a fruitfull collaboration :

  • A permanent contract on the basis of 39 hours/week with 10 floating days off per year in addition to paid vacation time,
  • Profit sharing (up to 10%),
  • Position based at our head office in Moirans (38) – near Grenoble.
  • Lunch voucher, nice premises, a great team that likes to share, many benefits with the Centr’alp card, monthly unformal team meetings, serious internal events but not only!
  • You don’t live in the Grenoble area? If you live in Paris area or in Paca, that’s fine too 
    Options open there, depending on profile and experience.

Your main responsibilities

As a key member of the design team (6 engineers), you will define SoC architectures and specify the blocks to be developed. You are involved in ASIC development at front-end level (Verilog and VHDL). You collaborate with the verification team as well as with the backend teams of our partners and customers.

You will be involved in one or two different projects per year, depending on their scope.

Is the job right for you?

In order to carry out your missions, you need to master several essential technical topics:

  • System-On-Chip architecture
  • Data Processing, Hardware Accelerators
  • RTL design (Verilog or VHDL , SystemVerilog design)
  • Multiple Clock Domain design, CDC

Other skills welcome:

  • STA / Timing Closure
  • AMBA (AXI, APB, AHB, …) and On-Chip-Interconnect bus expertise

Didn’t get a chance to get experience on those all? No problem! We are also a training organization and we will coach you on these topics to develop your expertise.

For an efficient and fruitful collaboration, we expect you to:

  • Have at least 2 years’ experience in digital design
  • Be able to balance between perfectionism and pragmatism!
  • Be eager to grow your skills and elaborate creative technical solutions,
  • Be able to work in a team,
  • Think “problem solving” and think “out of the box”,
  • Have an engineering background or equivalent.
  • Be eager to learn new things

Want to join us?

Our recruitment process is simple:

After an initial call, you’ll meet with Agnès, our HR Manager, and Christian, our Technical Director.

If your expectations match ours, the recruitment process concludes with a meeting with François, our CEO and founder.

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